This is an app created for VLSI Design knowledge sharing among the VLSI designers’ community. It is suitable for students learning VLSI design as well as VLSI designers. This app currently covers custom design and logic design. In logic design, knowledge sharing on verilog coding, ASIC synthesis, timing optimization in synthesis, testbenches, with lots of labs and examples to ease the learning process. In custom design, knowledge sharing on schematic capture, simulation, layout, DRC, LVS with lots of step by step guide, labs and examples.
This app also allow users to upload and share their knowledge sharing
articles. For experienced VLSI designers, you are most welcome to use this
feature to post articles on your knowledge sharing and experience in any